Field of the Invention
The invention lies in the field of semiconductor processing and relates, more specifically, to a method for fabricating a mask for forming structures in a semiconductor wafer.
Integrated semiconductor circuits are generally fabricated with the aid of planar technology. In the context of planar technology, the semiconductor wafers are nowadays patterned almost entirely with the aid of lithographic technology. An essential feature of this technology is the formation of a mask with the desired structure on the semiconductor wafer in order then to transfer the structure into the underlying layer of the semiconductor wafer in a subsequent process step, e.g. with the aid of an etching or an implantation. In this case, the mask generally comprises a thin radiation-sensitive layer, usually an organic photoresist layer, which is deposited on the semiconductor wafer. This thin radiation-sensitive layer is then irradiated in the desired regions, the irradiation generally being effected optically with the aid of a photomask. The photoresist layer that has been chemically altered by the radiation is then developed, wherein case, in positive resist technology, the photoresist decomposes at the exposed locations and the non-irradiated regions remain masked. In negative resist technology, in precisely the opposite fashion, the exposed locations are marked, while the unexposed resist is removed during development. The resulting pattern in the photoresist layer serves as a mask for the subsequent process step by means of which this pattern is then transferred into the underlying layer in the semiconductor wafer.
On account of the increasing miniaturization of the integrated circuits, it is necessary to image ever smaller structures with proportions of below 100 nm on the photoresist layer and then to transfer this pattern into the underlying layer of the semiconductor wafer. The lithographic production of such small structures is difficult particularly in regions with a dense arrangement of structures with dimensions in the region of the resolution limit of the optical exposure methods. This applies in particular to the fabrication of masks for trench or stacked capacitors in a memory cell array. Thus, during the imaging of small elongate structures, the so-called line shorting problem occurs, wherein patterns with significantly shortened lengths or widths are produced in the mask layer. Furthermore, in the case of very small structures, the problem of so-called corner rounding arises, wherein, instead of the desired edges, round corners are formed in the resist pattern as a result of the exposure at the resolution limit.
In order to combat these problems in the formation of masks for small structures, the structures are often imaged on the mask layer in such a way that the imaging errors are already taken into account. Thus, in accordance with so-called mask biasing, the structures to be imaged are intentionally lengthened relative to the desired structure or the mask is drawn with additional auxiliary structures which compensate for the imaging errors from the outset. However, this necessitates a complicated mask design, and the risk of imaging errors still exists.
It is accordingly an object of the invention to provide a method of fabricating a mask which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which allows a mask pattern to be reliably fabricated even for very small structures.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of fabricating a mask, which comprises the following method steps:
a) depositing a sacrificial layer on a semiconductor wafer;
b) processing the sacrificial layer in a first lithographic process sequence for patterning the sacrificial layer with a first pattern;
c) processing the sacrificial layer in a second lithographic process sequence for patterning the sacrificial layer with a second pattern;
d) applying a hard mask layer to completely enclose the sacrificial layer patterned in steps b) and c); and
e) removing the sacrificial layer from the hard mask layer.
In other words, according to the invention, in order to create a mask, firstly a sacrificial layer is applied on a semiconductor wafer, this sacrificial layer is then patterned with the aid of two successive lithographic process sequences, the sacrificial layer being processed for the purpose of forming a first mask pattern with the aid of the first lithographic process sequence and the sacrificial layer being processed for the purpose of forming a second mask pattern with the aid of the second lithographic process sequence, a hard mask layer is then applied in order to completely enclose the patterned sacrificial layer and the sacrificial layer is subsequently removed again laterally from the hard mask layer.
The method according to the invention makes it possible to produce a hard mask in the case of which even very fine structures packed extremely densely are imaged in a dimensionally accurate manner. Therefore, the method according to the invention is suitable in particular for the fabrication of integrated circuits with DRAM modules. The problems of line shortening and corner rounding can be avoided through the formation of an inverted mask with the aid of a sacrificial layer, which is furthermore subjected to a double lithography process, wherein a first line pattern is produced in a first direction and then a second line pattern is produced in a second direction. The mask fabrication technique according to the invention furthermore ensures that a hard mask of extremely uniform thickness is produced, thereby reliably avoiding damage to the mask during the transfer of the mask pattern into the underlying layer.
In accordance with an added feature of the invention, the sacrificial layer is processed in the successive lithography processes in two mutually perpendicular directions with a strip pattern in each case. As a result, rectangular structures, in particular capacitor structures in DRAMs, can be produced in a dimensionally accurate manner with exact edges.
In accordance with an additional feature of the invention, an etching stop layer is provided between the sacrificial layer and the semiconductor wafer, and etching processes for the sacrificial layer can be reliably stopped by means of the etching stop layer. This additional etching layer avoids the situation where the layer lying under the sacrificial layer is damaged in the context of the processing of the sacrificial layer.
In accordance with a further preferred embodiment, an additional intermediate mask layer is provided under the sacrificial layer, which is patterned in accordance with the pattern of the hard mask layer that is uncovered by the removal of the sacrificial layer. The use of this additional intermediate mask layer makes it possible to embody a highly exact uniform mask for subsequent patterning processes of the semiconductor layer lying under the intermediate mask layer.
According to the invention, it is also advantageous, during the application of the hard mask layer, to deposit the hard mask layer over the whole area in order to completely bury the patterned sacrificial layer and then to planarize the hard mask layer preferably with the aid of chemical mechanical polishing in order to uncover the surface of the patterned sacrificial layer. This ensures that a hard mask layer with high uniformity with regard to the thickness is produced and, at the same time, the sacrificial layer to be removed with the inverted mask structure is completely uncovered.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a mask for semiconductor structures, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.